One use for trench capacitors is for the storage node of dynamic random access memory (DRAM) cells. As DRAM cell design rules become ever smaller, the required cell capacitance does not become smaller proportionally but remains relatively fixed. The use of bottle trench capacitors is one way of increasing the capacitance trench capacitors as the dimensions of DRAM cells decrease. However, present schemes for forming bottle trench capacitors suffer from etch related defects during formation of the bottle portion of the capacitor. These defects can cause shorting of the capacitor to the P-well of the DRAM cell and/or uneven capacitor dielectric formation. Further, poor bottle diameter size control due to non-uniform wet etch processes can lead to irregular bottle diameter, often resulting in merging of the bottles of adjacent DRAM cells. Merging of adjacent the bottles of adjacent trench capacitors can cause single bit fails in DRAM cell arrays. Defects and merged trenches can reduce DRAM processing yield, reliability and performance. Therefore, there is a need for a bottle trench capacitor process with reduced susceptibility to process defects and merging of adjacent trenches during formation of the bottle portion of the capacitor.